1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and, more specifically, to a method of forming a low-dielectric constant material with good mechanical strength and a structure having a low-dielectric constant material with good mechanical strength.
2. Discussion of Related Art
Transistors are typically fabricated on a chip by using a substrate of semiconductor material, such as Silicon, and electrically insulating material, such as Silicon Oxide or Silicon Nitride. The transistors are subsequently wired with electrically conducting material, such as Aluminum or Copper, that are stacked in multiple layers and separated by electrically insulating material.
In 1965, Gordon Moore first suggested that the number of transistors per unit area on a chip could be doubled every 18 months. Over the ensuing decades, the semiconductor industry has adhered closely to the so-called Moore's Law. Maintaining such a schedule for each device generation, or technology node, has required continual enhancements to the processes of photolithography and etch to reduce the critical dimension (CD) that may be successfully patterned in the features across the chip. In addition, significant improvements had to be made to desired doping profiles and film thicknesses across the chip.
Photolithography was able to keep up with the reduction in CD needed for each device generation. However, improving the resolution usually required sacrificing the depth of focus (DOF). The process window would be large enough only if the smaller DOF could be countered by a reduction in topography at the surface of the substrate in which the transistors are being formed. Thus, chemical-mechanical polish (CMP) became an enabling technology for both the front-end and the back-end of semiconductor processing.
In order to improve device density, both the transistor in the front-end of semiconductor processing and the wiring in the back-end of semiconductor processing have to be scaled down. The scaling of the transistor and the wiring must be carefully balanced to prevent limitation of the switching performance. The switching performance of the transistor may be degraded by excessively large resistance-capacitance (RC) product delay in the wiring. Resistance in the wiring may be reduced by using electrically conducting material having a lower resistivity. Capacitance in the wiring may be reduced by using an electrically insulating material with a lower dielectric constant (k).
However, an electrically insulating material with a low dielectric constant may not be strong enough to withstand CMP.
Thus, what is needed is a method of forming a low-dielectric constant material with good mechanical strength and a structure having a low-dielectric constant material with good mechanical strength.